EU PVSEC Programme Online
EU PVSEC 2021, 6 - 10 September 2021
Presentation: 2AP.1.1 Perfecting Silicon
Type: Plenary
Date: Monday, 6th September 2021
08:30 - 09:30
Author(s): M. Boccard, V. Paratte, L. Antognini, J. Cattin, J. Dréon, D. Fébba, W. Lin, J. Thomet, D. Türkay, C. Ballif
Presenter / Speaker: M. Boccard, EPFL, Neuchâtel, Switzerland
Event: Conference Conference
Session: 2AP.1 Devices in Evolution: Pushing the Efficiency Limits and Broadening the Technology Portfolio
Topic: 2. 3 Low Temperature Route for Si Cells
Summary / Abstract: We review several strategies enabling high-efficiency silicon heterojunction solar cells, and perform a loss-analysis to identify routes for further improvements. Identifying parasitic absorption in the front contact as a main source of loss, weinvestigate,with simulations and experiments,local contacts on the front-side of silicon heterojunction (SHJ) solar cells.We evidence that state-of-the-art values ofcontact resistancereached in nowadays devices enable to localize current extraction over a few percent of the area only, without inducing prohibitive series-resistance increase.Furthermore,lateral transport of chargesthrough the wafer itself issufficient to suppress the transparent conductive oxide(wafer sheet resistances below 100 Ohm.square for electron transport). Simulations suggest that theoptimal coverage for the hole-selective contacts is around50% of the total area (around each finger), whereas values below 10% can be used for the electron contact. Preliminary experimental results confirm that a partial-contact architecture can be usedwithaminimal impact on the series resistance, enabling FF > 78% and series resistance < 1 Ω.cm2.