EU PVSEC Programme Online
EU PVSEC 2020, 7 - 11 September 2020
Presentation: 2BO.4.1 Multilevel Improvement in the Window Layers Stack of Silicon Heterojunction Solar Cell
Type: Oral
Date: Tuesday, 8th September 2020
15:15 - 16:45
Author(s): L. Antognini, V. Paratte, M. Truong, J. Cattin, J. Haschke, J. Dréon, L.-L. Senaud, G. Christmann, S. Nicolay, B. Paviet-Salomon, M. Despeisse, C. Ballif, M. Boccard
Presenter / Speaker: L. Antognini, EPFL, Neuchâtel, Switzerland
Event: Conference Conference
Session: 2BO.4 Si-Alloy Based Functional Layers and TCOs
Type(s) of Access:  Conference Registration
Topic: 2. 3 Low Temperature Route for Si Cells
Summary / Abstract: Silicon heterojunction (SHJ) is a proven technology for large-scale production of cost-effective high-efficiency photovoltaic modules. With progress in homojunction (PERC) and high-temperature passivating contact technologies, continuous efficiency improvement is still needed for this technology to keep its relevance. Standard SHJ design uses amorphous silicon (a-Si) for both passivation and selective layers, completed by ITO for lateral transport and antireflective coating (ARC). Such design allows baseline efficiency of 23%, in several laboratories and production industry [1]. We propose here a three-level optimizations of the front hole-contact stack to bring SHJ cell efficiency beyond 24% that is easy to integrate in the existing process flow. The sample architecture and the optimization roadmap is shown in Fig.1. The first step is to replace the (p) a-Si layer by nanocrystalline silicon (nc-Si)—and eventually nc-SiO—to improve contact resistance (c) and transparency [2]. Next, replacing ITO with higher-mobility IZrO enables higher transparency and conductivity. Finally, thinning the IZrO layer and capping it with a SiOx layer allows both to boost the transparency and conductivity, while reducing indium consumption.