Solar cells with amorphous silicon PIN radial junctions deposited on silicon nanowire (NW) arrays have recently reached the record efficiency of 9.7 %1, which is only slightly below the record efficiency of 10.2 % for a-Si:H solar cells2. NWs naturally introduce texturing which improves light absorption; however, they are also enlarging the area of PIN junction, thus increasing charge carrier recombination due to defects at interfaces. Further improvement of the efficiency of the solar cells based on Si NWs requires improved control and understanding of important loss mechanisms in the solar cells. We have studied PECVD fabrication of Si NW arrays under various deposition conditions. Layers of catalytic tin or indium metal nanoparticles on Corning glass with sputtered Al:ZnO thin films have been prepared by vacuum evaporation and a dewetting process at elevated temperatures. The plasma-assisted VLS-like growth works for all of those catalytic metals at temperatures around 400 °C; however, each of them requires quite different deposition conditions. Silicon nanowires typically with a thicknesses of tens of nm and lengths of microns have grown after few minute silicon deposition.